1. Field of the Invention
The present invention relates to a comparator circuit. More particularly, it relates to a comparator circuit comprising a differential stage and an output stage, which circuit is usually constructed by a semiconductor integrated circuit.
2. Description of the Related Art
Generally, in a comparator circuit comprising a differential stage and an output stage, a first input signal having a reference level and a second input signal having a level to be compared with the reference level are input to each of a pair of terminals, and an output signal having a level which is determined in accordance with the level of the second input signal is output from an output terminal. Also, the output signal of the differential stage is supplied to the output stage, through which the output signal of the differential stage is inverted and amplified.
In such a prior art comparator circuit, if it is assumed that the level of the second input signal becomes higher than the level of the first input signal and the voltage level difference between these two input signals increases, a transistor provided in the differential stage and having a gate to which the first input signal is supplied approaches a cut-off state. Thus, the output voltage level of the differential stage gradually rises, and finally, a transistor (P channel type) provided in the output stage and having a gate to which the output signal of the differential stage is supplied is brought to the cut-off state.
After such a cut-off state of the above transistors has occurred, if the level of the second input signal falls and becomes lower than the level of the first input signal, it is necessary to turn on the above transistors in the cut-off state. However, as a stray capacity usually exists in the semiconductor device, a long time is needed to turn on the above transistors due to the time for charging the stray capacity. Therefore, a problem arises in that the operational speed of the comparator circuit is remarkably delayed, especially when the level of the second input signal falls from high level to low level.